Verilog using Xilinx Vivado

This intermediate course in implementing Digital Logic functions for FPGA focuses on learning Digital logic design using Verilog HDL and how to use Xilinx Vivado design implementation tools and Integrated logic analyzer for verification on hardware. Also, you will learn how to write testbenches to test your FPGA Design before porting on an FPGA device. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.

Who Should Attend?

System engineers, system designers, logic designers and experienced hardware engineers interested in Verilog HDL design training who are implementing Digital logic algorithms using the Xilinx® Vivado® software and want to use Xilinx® Vivado® Design Suite for FPGA design.

Prerequisites

• Basic understanding of Digital Electronics Circuits.

Skills Gained

After completing this comprehensive training, you will know how to:

• Understand Vivado Design Suite flow for Digital System Design.
• Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation.
• Fundamentals of Verilog Programming that will help to ace an engineer.
• Different Modeling Styles in Hardware Description Language.
• List various low-level and high-level modeling blocks.
• IP integrator Design flow of the Vivado.
• How to write an RTL for Synthesis
• Writing Verilog Test benches.
• How to use Xilinx IPs.
• Hardware Debugging in Vivado viz. Integrated Logic Analyzer, Virtual I/O.
• Run hardware verification.
• Design of some real-world projects such as 7-segment display, I2C, SPI, UART Interface, for Development boards and many more.
• From Zero to Hero in Digital Design and Verilog HDL
• Common Interview Questions.