DSP FPGA using Xilinx System Generator

This intermediate course in  implementing DSP functions focuses on learning how to use System Generator for DSP, design  implementation tools and hardware co-simulation verification. Through hands-on exercises,  you will implement a design from algorithm concept to hardware verification by using Xilinx  FPGA capabilities.

Who Should Attend? 

System engineers, system designers, logic designers and experienced hardware engineers  interested in DSP design training who are implementing DSP algorithms using the MathWorks  MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design.

Prerequisites 

• Basic understanding of signal processing theory.
• Advantage if experience with the MATLAB and Simulink software.

Skills Gained 

After completing this comprehensive training, you will know how to:

• Describe the System Generator design flow for implementing DSP functions
• Identify Xilinx FPGA capabilities and implement a design from algorithm concept to  hardware simulation
• List various low-level and high-level functional blocks available in System Generator ● Run hardware co-simulation
• Identify the high-level blocks available for FIR and FFT designs
• Implement multi-rate systems in System Generator
• Integrate System Generator models into the Vivado IDE
• Design a processor-controllable interface using System Generator for DSP
• Generate IPs from C-based design sources for use in the System Generator environment